Problem creating "make clean"

Dear Rooters

I have two makefiles, named Makefile4MyClassA and Makefile4MyClassBC, which I include in a makefile (see attachments):

Sorrowly, when running “make clean” I get the following error:

Makefile4MyClassBC:76: warning: overriding commands for target .cxx.o' Makefile4MyClassA:76: warning: ignoring old commands for target.cxx.o’
make: clean-MyClassA: Command not found
make: *** [clean] Error 12

Why is clean-MyClassA not recognized?
How can I avoid the two warnings?

Thank you in advance
Best regards
Makefile.txt (151 Bytes)
Makefile4MyClassBC.txt (1.78 KB)
Makefile4MyClassA.txt (1.72 KB)

Instead of [code]clean::

@rm -f $(OBJS) core


you meant:

But I actually think this are redundant (you already have it in the respective makefile)


Dear Philippe

Thank you, but sorrowly this results in the following error:

Makefile4MyClassBC:76: warning: overriding commands for target `.cxx.o'
Makefile4MyClassA:77: warning: ignoring old commands for target `.cxx.o'
make: *** No rule to make target `clean-MyClassBC', needed by `clean'.  Stop.

Interestingly, libMyClassBC is always cleaned but not libMyClassA. Probably, because “include Makefile4MyClassBC” is called after “include Makefile4MyClassA”.

Meanwhile, I have found the following solution, but I think that this solution is not the way it should be done in a makefile:

	make -f Makefile4MyClassBC clean
	make -f Makefile4MyClassA  clean

Best regards

Yes indeed … the problem is that both of your makefile use the exact same variables … hence their over-ridden by the 2nd include … and your clean target are written using those variables … so clean-MyClassA is called but does not do what you expect.

Conclusion do NOT really on doing

include Makefile4MyClassA include Makefile4MyClassBC


Thank you, now I understand,