Hi Everyone,
I wanna use a compiled code, but I don’t know why if do [quote] make[/quote] it doesn’t compile, but got this errors:
g++ -g -std=c++11 -Wall -I/include -c -o Analyse.o Analyse.C
cc1plus: erreur: option "-std=c++11" de la ligne de commande non reconnue
make: *** [Analyse.o] Erreur 1
the Makefile is :
# Lines starting with the pound sign are comments.
#
# These are the two options that may need tweaking
EXECUTABLE = Analyse
LINKCC = $(CXX)
INCLUDES = -I$(ROOTSYS)/include
# You can modify the below as well, but probably
# won't need to
#
# CC is for the name of the C compiler. CPPFLAGS denotes pre-processor
# flags, such as -I options. CFLAGS denotes flags for the C compiler.
# CXXFLAGS denotes flags for the C++ compiler. You may add additional
# settings here, such as PFLAGS, if you are using other languages such
# as Pascal.
CPPFLAGS =
LDFLAGS = -L$(ROOTSYS)/lib `root-config --glibs`
#SOURCES=main_llllTree.cpp llllTree2.C
CC = gcc -g -std=c++11
CC = gcc -g
#CFLAGS = -Wall -O2
CFLAGS = -Wall
CXX = g++ -g -std=c++11
CXXFLAGS = $(CFLAGS) $(INCLUDES)
SRCS := $(wildcard *.c) $(wildcard *.cpp) $(wildcard *.C)
OBJS := $(patsubst %.c,%.o,$(wildcard *.c)) \
$(patsubst %.cpp,%.o,$(wildcard *.cpp)) \
$(patsubst %.C,%.o,$(wildcard *.C))
DEPS := $(patsubst %.o,%.d,$(OBJS))
# "all" is the default target. Simply make it point to myprogram.
all: $(EXECUTABLE)
# Define the components of the program, and how to link them together.
# These components are defined as dependencies; that is, they must be
# made up-to-date before the code is linked.
$(EXECUTABLE): $(DEPS) $(OBJS)
$(LINKCC) $(LDFLAGS) -o $(EXECUTABLE) $(OBJS)
# Specify that the dependency files depend on the C source files.
%.d: %.c
$(CC) -MM $(CPPFLAGS) $< > $@
$(CC) -MM $(CPPFLAGS) $< | sed s/\\.o/.d/ >> $@
%.d: %.cpp
$(CXX) -MM $(CXXFLAGS) $(CPPFLAGS) $< > $@
$(CXX) -MM $(CXXFLAGS) $(CPPFLAGS) $< | sed s/\\.o/.d/ >> $@
%.d: %.C
$(CXX) -MM $(CXXFLAGS) $(CPPFLAGS) $< > $@
$(CXX) -MM $(CXXFLAGS) $(CPPFLAGS) $< | sed s/\\.o/.d/ >> $@
# Specify that all .o files depend on .c files, and indicate how
# the .c files are converted (compiled) to the .o files.
clean:
-rm $(OBJS) $(EXECUTABLE) $(DEPS) *~
explain:
@echo "The following information represents your program:"
@echo "Final executable name: $(EXECUTABLE)"
@echo "Source files: $(SRCS)"
@echo "Object files: $(OBJS)"
@echo "Dependency files: $(DEPS)"
depend: $(DEPS)
@echo "Dependencies are now up-to-date."
-include $(DEPS)
I attached the others files which are in the same folder than Makefile.
I would really appreciate if someone could help please.
Cheers
llllTree2.h (190 KB)
llllTree2.C (2.1 KB)
Analyse.C (5.05 KB)